//time_count 模块
module time_count(
	input				sys_clk,
	input 				sys_rst_n,
	
	output	reg[19:0]	data,		//6位数码管要显示的数值
	output	reg[ 5:0]	point,		//小数点 在本次实验不需要显示
	output	reg			en,			//数码管使能信号
	output	reg			sign		//符号位，高电平显示符号，低电平显示正号
);

//parameter define	
parameter	MAX_NUM = 23'd5000_000;	//计数器最大值

//reg	define
reg [22:0]	delay_cnt;
reg			flag;


//计数器对系统时钟计数达到10ms时，输出一个时钟周期的脉冲信号
always @(posedge sys_clk or negedge sys_rst_n)	begin
	if(!sys_rst_n)	begin
		delay_cnt <= 23'b0;
		flag <= 1'b0;
	end		
	else if (delay_cnt < MAX_NUM - 1'b1) begin
        delay_cnt <= delay_cnt + 1'b1;
        flag <= 1'b0;
    end
    else begin
        delay_cnt <= 23'b0;
        flag <= 1'b1;
    end
end 

//数码管显示数据 从0到999999
always @(posedge sys_clk or negedge sys_rst_n)	begin
	if(!sys_rst_n)	begin
		data	<= 20'd0;
		point 	<= 6'b00_0000;
		en 		<= 1'b0;
		sign 	<= 1'b0;
	end
	else	begin
		point 	<= 6'b00_0000;
		en 		<= 1'b1;
		sign 	<= 1'b0;
		if(flag)	begin
			if(data < 20'd999999)
				data <= data +1'b1;
			else
				data <= 20'b0;
		end
	end
end

endmodule
